The invention relates to a data buffering system in a computer or digital communication system, and deals more particularly with a data buffer between two data buses.
A computer system comprises in most cases bus systems and bus architectures with different characteristics. Such bus systems or bus architectures have, for instance, different clock and transfer frequencies, operate synchronously or asynchronously, have a different number of lines, a different data flow width, and also a different length. They are connected to each other in a data processing system by coupling circuits and, if necessary, by buffers with interface circuits. The coupling circuits themselves may also comprise buffers for adapting the speed differences of the different bus systems or buses. For transferring, for example, data in a computer system from one bus to another, for which purpose the first bus is associated with the processor and its storage and the second bus with various input/output devices, the data is initially fed to the coupling circuit and thence, for example, to the associated input/output device terminal, keeping the delay by the coupling circuit to a minimum.
Data buffers with a so-called ping-pong data buffer mechanism for transferring data within a computer system from one data bus to another are known, for example, from the European patent application 0 416 281 A2. This mechanism contains a dual port storage mechanism consisting of a storage array and two independent ports, with each port having its own separate data buses, address buses and control buses, as well as the circuits associated therewith. In this known data buffer, the write circuit is coupled to an independent port for receiving data from one of the data buses, in order to write this data into the first part of the storage array. The read circuits in this buffer are coupled to the other independent ports for simultaneously reading from the second part of the storage array, with the read data being transferred to the other data bus. In conjunction therewith, an operating control logic is described which is capable of performing the read and write functions for the first and the second part of the storage array in both directions. In addition, a circuit example is described, wherein a pair of a dual port storage mechanism serves to transfer data, and wherein the first bus has a larger data width and the second bus has a smaller data width.
Furthermore, IBM TDB, Volume 27, No. 1A, June 1984, pp. 334 to 337, describes a circuit arrangement which also comprises a data buffer between two different data bus systems. Although this article describes a typical solution to the problem of how data may be transferred between two data bus systems with different characteristics, the use of a dual port buffer is relatively elaborate from a technical point of view. The control circuits described also involve a large number of technical circuit means.
Therefore, it is the object of the invention to provide a control circuit and an operating method for a buffer of a data or information processing system, wherein the data buses or data bus systems to be connected to each other through the data buffer have different clock frequencies and other different characteristics.
Another object is to improve the type of write address pointer employed--also implemented as a load counter in a circuit--, i.e. the use of the code, its generation, and the resetting of the pointer, considering that the clock pulse sequences of the two buses are not interconnected.